1. Technical Field
The present invention relates to timing verifications for integrated circuit designs in general, and in particular to a method for synthesizing relative timing constraints on an asynchronous circuit design to facilitate the performance of timing verification on the asynchronous circuit design.
2. Description of Related Art
Asynchronous circuit and protocol designs typically require formal verification in order to ensure the designs can behave correctly under all operating conditions. As part of the performance and timing validation computer-aided design tool flow, relative timing is commonly utilized to verify asynchronous circuit and protocol designs that they are capable of producing certain desirable results. However, most asynchronous circuit and protocol designs cannot be proven of their conformance to their respective specifications during timing verification without the addition of certain relative timing constraints to the design beforehand.
Today, the process of generating path-based relative timing constraints for an asynchronous circuit and/or protocol design for the purpose of timing validation is typically performed manually by a verification engineer with good intuition and exquisite knowledge of asynchronous circuit designs via the aid of a formal verification engine. Suffice to say, such manual process is as time-consuming as it is error-prone. For example, some asynchronous circuit designs can take up to five hours for an expert verification engineer to create a sufficient set of relative timing constraints.
Consequently, it would be desirable to provide an improved method for automatically generating relative timing constraints on an asynchronous circuit or protocol design for the purpose of timing verification.